Hierarchy	Input	Constant Input	Unused Input	Floating Input	Output	Constant Output	Unused Output	Floating Output	Bidir	Constant Bidir	Unused Bidir	Input only Bidir	Output only Bidir
control|address_	130	128	0	128	32	128	128	128	0	0	0	0	0
control|data	130	0	0	0	32	0	0	0	0	0	0	0	0
control|sub|a2	3	0	0	0	2	0	0	0	0	0	0	0	0
control|sub|a1	3	0	0	0	2	0	0	0	0	0	0	0	0
control|sub|a0	3	0	0	0	2	0	0	0	0	0	0	0	0
control|sub	7	4	0	4	3	4	4	4	0	0	0	0	0
control	131	0	0	0	66	0	0	0	0	0	0	0	0
stage2_1|odd|a31	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a30	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a29	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a28	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a27	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a26	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a25	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a24	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a23	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a22	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a21	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a20	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a19	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a18	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a17	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a16	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a15	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a14	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a13	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a12	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a11	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a10	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a9	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a8	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a7	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a6	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a5	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a4	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a3	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a2	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a1	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd|a0	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|odd	66	2	0	2	32	2	2	2	0	0	0	0	0
stage2_1|even|a31	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a30	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a29	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a28	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a27	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a26	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a25	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a24	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a23	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a22	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a21	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a20	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a19	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a18	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a17	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a16	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a15	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a14	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a13	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a12	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a11	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a10	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a9	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a8	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a7	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a6	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a5	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a4	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a3	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a2	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a1	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even|a0	3	0	0	0	2	0	0	0	0	0	0	0	0
stage2_1|even	66	2	0	2	32	2	2	2	0	0	0	0	0
stage2_1|temp|add_1|CLA_4bits_2	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block7|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block7|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block7|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block7|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block7|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block7	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block6|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block6|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block6|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block6|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block6|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block6	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block5|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block5|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block5|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block5|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block5|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block5	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block4|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block4|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block4|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block4|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block4|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block4	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|CLA_4bits_1	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block3|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block3|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block3|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block3|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block3|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block3	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block2|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block2|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block2|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block2|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block2|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block2	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block1|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block1|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block1|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block1|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block1|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block1	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block0|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block0|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block0|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block0|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block0|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|add_1|block0	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|add_1	66	2	0	2	32	2	2	2	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|CLA_4bits_2	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block7|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block7|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block7|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block7|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block7|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block7	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block6|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block6|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block6|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block6|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block6|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block6	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block5|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block5|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block5|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block5|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block5|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block5	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block4|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block4|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block4|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block4|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block4|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block4	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|CLA_4bits_1	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block3|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block3|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block3|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block3|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block3|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block3	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block2|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block2|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block2|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block2|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block2|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block2	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block1|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block1|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block1|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block1|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block1|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block1	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block0|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block0|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block0|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block0|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block0|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds|block0	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[31].adds	66	3	0	3	32	3	3	3	0	0	0	0	0
stage2_1|temp|M_3|o[30].adds|CLA_4bits_2	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[30].adds|block7|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[30].adds|block7|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[30].adds|block7|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[30].adds|block7|FA_1	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[30].adds|block7|FA_0	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[30].adds|block7	10	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[30].adds|block6|CLA_4bits_0	9	0	0	0	6	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[30].adds|block6|FA_3	4	0	0	0	3	0	0	0	0	0	0	0	0
stage2_1|temp|M_3|o[30].adds|block6|FA_2	4	0	0	0	3	0	0	0	0	0	0	0	0
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